EE G3900 VLSI Design for Testability Technology II
This course is geared towards understanding of IC and SoC design methodologies such as IBM's and TSMC's ASIC sign-off processes, full-and partial-scan insertions, boundary scan insertion, synthesis of BIST structures, robust delay testing, test resource management, the IEEE 1500 standard for SoC solutions, and other advanced topics such as low-pin count testing and mixed-signal testing. Students are required to perform design projects using CAD software systems such as Cadence Design System and SynTest Technologies' DEF solutions. The main outcome is the understanding of state-of-art technologies demonstrated through commercial CAD software systems, as well as learning and practicing industry solutions. Advanced students will be encouraged to explore new ideas in research projects.
Contact Hours
3 hr./wk.