EE G3800 VLSI Design for Testability Technology I
This course is to cover concepts such as Economics of IC Test, Methods of Test, Testability and Measurements, Fault Models and Simulation, Test Pattern Generation, LogicTest, Memory Test, the IBM Level Sensitive Scan Design (LSSD) methodology, General Scan Design (GDS) methodology, Partial-and Full Scan designs, the IEEE 1149 boundary scan standards. Along with lectures, homework assignments, and exams, students are required to conduct at least one DFT design project to demonstrate understanding of DFT principles and methods. The main outcome is the basic understanding of DFT concepts and methods.
Contact Hours
3 hr./wk.